Split gate non-volatile memory cell arrays are known. U.S. Pat. Nos. 6,747,310 and 7,868,375 disclose non-volatile memory cells having four gates (floating gate, control gate, erase gate and select gate). The conductive gates are typically formed of conductive polysilicon. It is also known to form logic devices on the same silicon chip. However, processing steps in forming the memory cells can adversely affect the previously fabricated logic devices, and vice versa. Moreover, as device geometries continue to shrink, the desired performance is difficult to achieve given the conductivity of the polysilicon material used to form the conductive gates. Lastly, modem applications could benefit from the formation of logic devices with different operational thresholds on the same chip (e.g. low and high voltage logic devices on the same semiconductor chip as that containing the memory cells).
As the logic transistors scale to advanced nodes with smaller feature sizes, new gate materials (such as high-k dielectric and metal gates discussed below) are needed. There is a need for an improved memory cell array and method of fabrication that includes memory cells, low voltage logic devices and high voltage memory devices on the same substrate, and with gates made of sufficiently conductive material.